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| Preliminary TSM4835 30V P-Channel MOSFET SOP-8 Pin Definition: 1. Source 2. Source 3. Source 4. Gate 5, 6, 7, 8. Drain PRODUCT SUMMARY VDS (V) RDS(on)(m) -30 18 @ VGS = -10V 30 @ VGS = -4.5V ID (A) -9.6 -7.5 Features Advance Trench Process Technology High Density Cell Design for Ultra Low On-resistance Block Diagram Application Load Switches Desktop PCs Notebook PCs P-Channel MOSFET Ordering Information Part No. TSM4835CS RL Package SOP-8 Packing 2.5Kpcs / 13" Ree Absolute Maximum Rating (Ta = 25oC unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Continuous Source Current (Diode Conduction) Maximum Power Dissipation Operating Junction Temperature Operating Junction and Storage Temperature Range a,b o o Symbol VDS VGS ID IDM IS PD Limit -30 25 -9.6 -50 -2.1 Unit V V A A A W o o Ta = 25 C Ta = 75 C 2.5 1.6 +150 - 55 to +150 TJ TJ, TSTG C C Thermal Performance Parameter Junction to Foot (Drain) Thermal Resistance Junction to Ambient Thermal Resistance (PCB mounted) Notes: a. Pulse width limited by the Maximum junction temperature b. Surface Mounted on FR4 Board, t 10 sec. Symbol RJF RJA Limit 18 39 Unit o o C/W C/W 1/1 Version: Preliminary Preliminary TSM4835 30V P-Channel MOSFET Electrical Specifications (Ta = 25oC unless otherwise noted) Parameter Static Drain-Source Breakdown Voltage Gate Threshold Voltage Gate Body Leakage Zero Gate Voltage Drain Current On-State Drain Current a a Conditions VGS = 0V, ID = -250uA VDS = VGS, ID = -250A VGS = 25V, VDS = 0V VDS = -30V, VGS = 0V VDS -5V, VGS = -10V VGS = -10V, ID = -9.6A VGS = -4.5V, ID = -7.5A VDS = -15V, ID = -9.6A IS = -2.1A, VGS = 0V Symbol BVDSS VGS(TH) IGSS IDSS ID(ON) RDS(ON) gfs VSD Qg Qgs Qgd Ciss Coss Crss td(on) tr td(off) Min -30 -1 ---50 --------------- Typ -----14 23 30 -0.8 25 6.5 12.5 2089 597 495 15 13 60 45 Max --3 100 -1.0 -18 30 --1.2 37 --2347 -624 25 20 100 70 Unit V V nA A A m S V Drain-Source On-State Resistance Forward Transconductance Diode Forward Voltage Dynamic b a Total Gate Charge Gate-Source Charge Gate-Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching c VDS = -15V, ID = -9.6A, VGS = -5V VDS = -15V, VGS = 0V, f = 1.0MHz nC pF Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time VDD = -15V, RL = 15, ID = -1A, VGEN = -10V, nS RG = 6 Turn-Off Fall Time tf Notes: a. pulse test: PW 300S, duty cycle 2% b. For DESIGN AID ONLY, not subject to production testing. b. Switching time is essentially independent of operating temperature. 2/2 Version: Preliminary Preliminary TSM4835 30V P-Channel MOSFET SOP-8 Mechanical Drawing DIM A B C D F G K M P R SOP-8 DIMENSION MILLIMETERS INCHES MIN MAX MIN MAX. 4.80 5.00 0.189 0.196 3.80 4.00 0.150 0.157 1.35 1.75 0.054 0.068 0.35 0.49 0.014 0.019 0.40 1.25 0.016 0.049 1.27BSC 0.05BSC 0.10 0.25 0.004 0.009 0 7 0 7 5.80 6.20 0.229 0.244 0.25 0.50 0.010 0.019 3/3 Version: Preliminary Preliminary TSM4835 30V P-Channel MOSFET Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC's terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale. 4/4 Version: Preliminary |
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